Rigid or flexible circuit boards are used for mounting and interconnecting electronic components in most electronic equipment. Typically, circuit boards have a plurality of laminated dielectric layers and a plurality of electrical interconnections formed with conductor path networks between or on the dielectric layers. It is necessary to test the integrity of electrical interconnections formed with conductor path networks in circuit boards before shipment so as to ensure the quality of circuit boards. The integrity of electrical interconnections formed with the conductor path networks in circuit boards means that the circuit boards are free from one or more defects, such as, an “open circuit” defect having substantially infinite resistance or unacceptable large value of resistance between two points which are intended to be connected by conductor paths and a “short circuit” defect having unacceptable low value of resistance between two independent networks of conductor paths which are intended to have no electrical connection. The value of substantially infinite resistance in an open circuit defect and the unacceptable low value of resistance in a short circuit defect would vary depending on applications of circuit boards.
A prior art method and apparatus for testing circuit boards involve using at least one pair of moving metal probes to electrically contact with each terminal provided on the surfaces of circuit boards for connecting to conductor path networks, and making resistance measurements between a pair of terminals each interconnecting the same conductor path network to verify the existence of the conductive path network, that is, the absence of open circuits in a conductive path network, and resistance measurements between a terminal of each interconnecting a conductor path network and a terminal of all the other interconnecting conductor path networks to ensure the absence of short circuits.
The disadvantage of this prior art resistance measurement method and apparatus is that it requires a large number of individual measurements. For example, in a circuit board having the number N of networks and the number P of terminals, the number (P−N) of resistance measurements is required for verifying the absence of open circuits in any conductive path in the board. In addition, the number {N×(N−1)}/2 of resistance measurements is required for verifying the absence of short circuits between any of independent networks in the board. Therefore, the total number (P−N)+{N×(N−1)}/2 of resistance measurements is required for testing the integrity of electrical interconnections of conductive path networks in a circuit board. This resistance measurement test takes a long time for verifying the integrity of electrical interconnections of circuit boards.
In order to solve this problem of the prior art resistance measurement test, Japanese Published Examined Patent Application (JAPEPA) No. 57-30227 and U.S. Pat. No. 4,565,966 provide method and apparatus for testing circuit boards by capacitive measurements. The capacitive measurement by JAPEPA No. 57-30227 measures the capacitance between conductor paths connected to each terminal and an internal conductive reference plane of a circuit board. The capacitive measurement by U.S. Pat. No. 4,565,966 measures the capacitance between conductor paths connected to each terminal and an external conductive reference plane attached to a circuit board under test. All terminals connected to the same conductor path network will show very nearly the same capacitance value. In the case of an “open circuit” defect, one or more of the terminals will show a capacitance value below the norm for the network thus indicating a conductor connected thereto which is shorter than it should be. “Short circuit” defect, that is, a connection between two independent networks, results in abnormally high capacitance values at all terminals belonging to the shorted networks. According to these capacitance measurements, the total number N of capacitance measurements is only required for testing the integrity of interconnection of conductor path networks in a circuit board having the number N of networks and the number P of terminals. Therefore, these capacitive measurements can drastically reduce time taken for testing the integrity of electrical interconnections of circuit boards.
However, JAPEPA No. 57-30227 requires an internal conductive reference plane covering over entire networks in a circuit board for capacitance measurements. U.S. Pat. No. 4,565,966 requires an external conductive reference plane covering over entire networks and attached to one surface of a circuit board to be tested for capacitance measurements.
For the conventional capacitance measurement disclosed by JA PEPA 57-30227, it is impossible to test the integrity of electrical interconnections of a circuit board which does not have an internal conductive reference plane covering over entire networks in the circuit board because capacitance values would not change enough to detect any defect when there is a defect, such as an open circuit and a short circuit defects, in a network which is not covered by the reference plane.
In the other conventional capacitance measurement disclosed by U.S. Pat. No. 4,565,966, an external conductive reference plane is required to be attached to one surface of a circuit board. Therefore, test must be performed through terminals exposed on the other surface of the circuit board to which the external conductive plane is not attached. In other words, test must be performed twice for a circuit board if the circuit board has terminals to be tested on two opposite surfaces of the circuit board. Accordingly, time taken for the capacitance measurement test gets longer. In addition, if the surface of a circuit board has a curvature or a circuit board has a different thickness, an external conductive reference plane cannot be attached to the surfaces of the circuit board with uniform distance with respect to a conductor path provided in a circuit board. Accordingly, capacitance measurement values between an external conductive reference plane and a conductor path in a circuit board would vary due to the curvature of the surface of a circuit board to which an external conductive reference plane is attached and/or the different thickness of a circuit board between an external conductive reference plane and a conductor path in a circuit board. Therefore, it could not detect a defect in such a circuit board quickly and correctly.
In order to solve these drawbacks of conventional capacitance measurements as shown in the references, JA PEPA 57-30227 and U.S. Pat. No. 4,565,966, there is disclosed an article, Y. Hidehira, “Bare Board Tester with Moving Probes For BGA/CSP”, Electronic Material, Published by Kogyouchosakai, Vol. 38, No. 9, pp. 77˜81, September, 1999, which teaches a method comprising the steps of applying a radio frequency (RF) signal to a power plane, a ground plane or other wide conductor provided in a circuit board to be tested, detecting the RF signal from a terminal connected to a conductor path in the circuit board, and comparing a phase difference between the applied RF signal and the detected RF signal so as to detect an open circuit defect and/or a shirt circuit defect in the conductor path of the circuit board.
Although this prior art method solves the drawbacks of conventional capacitance measurements, it still requires a power plane, ground plane, or other wide conductor provided within a circuit board for applying a RF signal. Therefore, the prior art method cannot be used for circuit boards which do not have any power plane, ground plane or other wide plane therein. The phase difference between the applied RF signal and the detected RF signal is not large enough to detect quickly and accurately all kinds of defect in a circuit board.
Therefore, an object of the present invention is to provide a method and apparatus capable of solving the above-mentioned problems of the prior art so as to provide quick and accurate testing for circuit boards which do not have any power plane, ground plane or other wide plane therein.